Wafer level packaging (WLP) technology provides for the packaging of semiconductor devices at a wafer level. WLP is employed in a variety of technologies including 3D-integrated circuits (IC), chip scale package (CSP) devices, and micro electromechanical systems (MEMS).
Micro electromechanical systems (MEMS) devices are small electro-mechanical systems often incorporated into integrated circuit devices. The fabrication and development of products encompassing MEMS devices has experienced numerous challenges including those of integrating the MEMS chips and integrated circuit chips together. Typically the chips may be placed side-by-side and then wire bonded together, which provides a product with a large footprint. Wafer level chip scale packaging of MEMS and CMOS devices is advantageous in that it can reduce packaging and integration costs, however, other issues arise. Measures to increase WLP MEMS device yield and reduce WLP MEMS device manufacturing cost are continuously being sought.
Like reference symbols in the various drawings indicate like elements.